The need for digital audio and video (A/V) interfacing has increased with current consumer electronics devices. Applications include, for example, interfacing personal computer (PC) desktops with a variety of display monitors, DVD players or set-up boxes with television sets, A/V receivers with television sets, and PC desktops with television sets. A variety of digital interface protocols are in use. Such display interface protocols include, but are not limited to, Digital Visual Interface (DVI), High Definition Multimedia Interface (HDMI), and DisplayPort. Furthermore, since there is a need for multiple electronic devices to interface with one another, there is a need for multi-port switching between devices.
FIG. 1 illustrates a prior art Pixel-based video interface system 101. The video interface system 101 is used to transport a video stream from a video source 100 to a display device such as an LCD/Plasma display device 104. In the prior art video interface system 101, video source 100 includes devices such as PC graphics cards, DVD players, set-top-box or other similar devices. Display devices include CRT based monitors, TVs, or pixel based LCD/Plasma monitors or TVs. Between the video source 100 and display device 104 there is a video link 102. The video link 102 includes a video transmitter 106, video receiver 108 and a link media. Typical types of link media in a pixel-based video transport system include VGA (analog), DVI, LVDS and HDMI. The video receiver 108 includes a scaler 300 described in further detail below in reference to FIG. 3.
Video source 100 may have a variety of different operating specifications or formats. These specifications and formats include video source resolution, video pixel color depth, and video clock rate. For example, a SVGA video mode has a resolution of 800×600 and a video clock rate of 40 Mhz. An SXGA video mode has a resolution of 1280×1024 and a video clock rate of 108 Mhz. Pixel-based video interface system 101 transports the video stream using the source video rate 100 as the link rate 112 and transport one pixel per link clock cycle. Therefore the video link 102 in these prior art systems needs to operate over a wide range of link rates. This makes it difficult for pixel-based video link 102 to reach the high link rates required by a high rate video source 100. Furthermore, another limitation of pixel-based video link 102 is that it is not flexible for different display format or color depth since the pixels are tied to the link rate.
There has been a trend to use non-pixel based video interface systems in which the video link link rate is decoupled from the source video rate. This non-pixel-based video interface system provides a flexible solution to accommodate a wide range of video sources. One example of such a non-pixel-based video interface system that incorporates a packet based link system is DisplayPort. Unlike the pixel-based video link, DisplayPort uses a fixed link rate. The video source stream is transported over the link through the packet mechanism. FIG. 2 illustrates a prior art non-pixel based video interface system such as DisplayPort. The video interface system 201 is used to transport a video stream from a video source 200 to a display device such as an LCD display 204. In the prior art video interface system 201, video source 200 includes devices such as PC graphics cards, DVD players, set-top-box or other similar devices. Display devices include CRT based monitors, TVs, or pixel based LCD/Plasma monitors or TVs. Between the video source 200 and display device 204 there is a video link 202. The video link 202 includes a video transmitter 206, video receiver 208 and a link media such as Display Port. Video source 200 may have a variety of different operating specifications or formats. The non-pixel-based video interface system 201 transports the video stream at a fixed link rate 212 rather than the source video rate.
The advantages of this packet based video link include increased bandwidth, configurability, adoption ability and extension ability. The link is capable of carrying multiple video streams. HDMI 1.3 is another example of a packet based video link, where the link rate can be multiples of the source video rate in order to transport a video source stream with greater than 24-bit color depth.
With regard to display devices, pixel based display devices such as LCD panels or Plasma panel monitors and TVs, have a fixed display format and fixed display rate. For example, an XGA LCD panel has a fixed resolution of 1024×768 and a clock rate of approximately 65 Mhz. A 1080P LCD TV has a fixed resolution of 1920×1080 and a clock rate of 148 Mhz. In order to display a video source signal on this type of display device, a video scaler, usually composed of a big line buffer and a horizontal/vertical interpolator, is necessary to convert the source video format/rate to the destination display format/rate. The video scaler typically includes a big line buffer and a horizontal/vertical (H/V) interpolator.
In the prior art, there are several solutions to convert the source video format to the display format in pixel-based video interface systems. All these solutions, referred to as video scalers, require explicit source video clock and source video timing control signaling (also referred to herein simply as “timing control”), such as video horizontal sync, horizontal display enable, vertical sync, and vertical display enable signals. The explicit video clock and video timing control signaling is readily available because the interface is based purely on the clock and timing of video source. FIG. 3 illustrates a prior art video scaler 300 for a pixel-based video interface system. An input sampler 302 receives a source video stream 310 and video timing control signaling 312. Video scaler 300 uses a PLL 308 which is used to convert the source video clock 314 to the display clock 316. A line buffer 304 is a large temporary buffer to store the video source lines to bridge the timing between video source and display destination. A horizontal/vertical interpolator 306 does the interpolation to create the display data 318.
In performing the video format conversion, one prior art video scaler discussed in U.S. Pat. No. 5,739,867 employs linear scaling techniques. It pre-determines off-line the destination display clock frequency and destination horizontal total time to make the destination video timing linear to the source video timing. The merit of this solution is that it is simple to implement and requires a relatively small line buffer. But this solution has several drawbacks: (1) It requires a PLL to generate display clock 316 which needs to lock to source video clock 314, (2) The resulting destination video horizontal timing may violate the display timing specifications, (3) The resulting destination video vertical timing may violate the display timing specifications, and (4) The last line of the frame could be short line or long line, violating the display timing specifications.
Another prior art solution discussed in U.S. Pat. No. 7,034,812 uses a relatively larger line buffer and automatic tuning algorithm to search for the destination display line rate such that the line buffer over-run and under-run do not occur. This solution is more flexible in supporting different types of LCD monitors. However, it requires a larger buffer size and the auto tuning algorithm may take a long time to converge. Furthermore, the destination horizontal and vertical timing may also violate the LCD timing specifications.
Yet another prior solution discussed in U.S. Pat. No. 7,071,992 utilizes several techniques to bridge the different video format. Line buffer underflow or overflow issues are addressed by adjusting the output number of lines per frame or output number of pixels per line. Although solutions are provided to ensure the output video timing does not exceed the output device specifications, the solutions are based on the explicit input video timing. There are a few other solutions discussed in U.S. Patent Application, No. US2005/0078126 which are generally the variations of U.S. Pat. No. 5,739,867.
However, these prior solutions to convert the source video format to the display format discussed thus far cannot be directly applied to non-pixel based video interfaces as shown in FIG. 2. In non-pixel-based video interfaces, the source video clock and source video timing control are not directly available to the video receiver. Instead, this information may be embedded in the link data stream or link packet. Furthermore, an additional limitation is that the source video data stream received in the video link may not follow a strict source video timing. Instead, what is available in the link data is an isochronous data flow which only roughly reflects the source video timing. As a result, prior art solutions to convert the source video format to the display format in non-pixel based video interfaces require a two stage process as shown in FIG. 4. FIG. 4 illustrates a prior art two-stage video receiver.
In the first stage, the input video stream consisting of the source video data stream 418, source video timing control 420, and source video clock 422 carried over the link is recovered first using a link layer device comprising a link buffer 402 and a PLL1 404. This involves the use of PLL1 404 to recover the source video clock 422 from the link clock 416. The link buffer 402 is used to reconstruct source video timing control 420 and source video data stream 418. The second stage uses a conventional video scaler as shown in FIG. 3 to scale up or scale down the source video format into the desired destination display format. This involves a PLL 2 to generate the destination display clock 424 from the source video clock 422, and a video line buffer 408 to construct the destination display timing and data stream from the source video stream. This two-stage approach in which the source video clock, source video timing control, and source video data stream must be recovered requires several hardware resources. Furthermore, some of the hardware resources may perform duplicative or overlapping functions. For example, the link buffer in the first stage and the line buffer in the second stage basically do the same thing to temporally store the video data. Furthermore, the requirement of two PLLs in this solution increases the design complexity, increasing the silicon cost and power consumption.
Thus, there is a need for improved systems and methods for generating or reconstructing display streams in video interface systems.